1. Field of the Invention
This disclosure relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device that prevents a high voltage of a bitline from being discharged.
2. Description of the Related Art
Electrically-Erasable Programmable Read-Only Memories (EEPROMs) and flash EEPROMs, or flash memories, are convenient in that data can be electrically reprogrammable after erasing previous data is erased. Thus, they are widely used today. NAND flash memories are especially advantageous to achieving high integration densities relative to other commercial flash memories.
In general, a NAND flash memory has a cell array that includes a number of cell strings, each cell string constructed of memory cells connected in series. A single memory cell is formed of a control gate, a floating gate, and a source and drain in a bulk. The F-N (Fowler-Nordheim) tunneling effect is used to erase data by block (or sector) and to program data by page.
For example, when a NAND flash memory is programmed, a low voltage (e.g. 0V) is applied to the source and drain while a high voltage (e.g. over 15V) is applied to the control gate, so that electrons are injected into the floating gate from the bulk to raise a threshold voltage thereof. It is referred to as being written with data “0” (i.e., a programmed cell). When the flash memory is erased, a negative voltage is applied to the control gate while a high voltage is applied to the bulk, so that electrons move into the bulk from the floating gate to lower a threshold voltage thereof. It is referred to as being erased and as storing data “1” (i.e., an erased cell).
FIG. 1 is a cross-sectional diagram illustrating a cell string of a conventional NAND flash memory device. In the structure, a pocket P-well 3 is surrounded by an N-well 2 in a semiconductor substrate 1. Within the pocket P-well 3, which is formed at a predetermined depth in the N-well 2, N+ active regions are spaced apart from each other by channel regions therebetween.
When an erase voltage VER of high voltage level is applied to the bulk (the pocket P-well 3 and the N+ well 2), the erase voltage VER is coupled to a bitline BL through the forward bias of PN junctions between the pocket P-well 3 and the N+ active regions. As the erase voltage VER is about 20V, the transistors connected to the bitline BL must be able to endure this high voltage. Also, the erase voltage VER must be carefully managed to prevent it from being applied directly to low voltage circuits used in page buffers or bitline drivers.
FIG. 2 is a circuit diagram illustrating cell strings in a conventional NAND flash memory circuit that have a shielded bit line architecture as disclosed by U.S. Pat. No. 6,480,419 entitled “Bit line setup and discharge circuit for programming non-volatile memory.”
The circuit illustrated in FIG. 2 includes a cell array 10, a first high voltage circuit 20, a second high voltage circuit 30, a page buffer 40, and a bitline driver 50. The page buffer 40 and bitline driver 50 are operable with a power supply voltage Vcc.
The cell array 10 is composed of a number of cell strings connected to respective bitlines BLe0, BLo0, BLe1, and BLo1. While FIG. 2 illustrates four cell strings for convenience, it should be understood that there may be many more cell strings within the cell array 10 in accordance with practical dimensions of the flash memory device. Each cell string includes a string selection transistor, a ground selection transistor, and memory cells connected in series between the selection transistors. The string selection transistor, the memory cells, and the ground selection transistor are coupled to a string selection line SSL, wordlines WL0˜WLn-1, and a ground selection line GSL, respectively. The lines SSL, WL0˜WLn-1, and DSL carry outputs from a row decoder (not shown). The bitlines are connected to the page buffer 40 and the bitline driver 50.
In memory cell array structures that do not have the high voltage circuits 20 and 30, malfunctions may easily occur between adjacent bitlines because of increasing coupling capacitances between the bitlines as integration densities of the NAND flash memories become higher. In particular, a bitline biased to 0V may drop to a voltage of its adjacent bitline biased on the power supply voltage Vcc. This may cause a programming operation instability, which forces a memory cell that should be in an erase state to be programmed.
For the purpose of overcoming the above problem, shielded bitline architectures for flash memory devices have been proposed. In the shielded bitline architecture of FIG. 2, switching transistors NM0˜NM3 and NM4˜NM7 of the high voltage circuits 20 and 30 select an alternative one among the even-ordered bitlines BLe0 and BLe1 or among the odd-ordered bitlines BLo0 and BLo1, during a read operation or a programming operation. While selected bitlines are conductive during a read operation or during a programming operation, deselected bitlines act as shielding means for the selected bit lines to reduce the coupling effects between the selected bitlines.
However, even with the shielded bitline architecture, a high voltage applied to the bitlines may still be discharged toward the page buffer 40 or the bitline driver 50. This will become more apparent with reference to FIGS. 3 and 4 that are explained in further detail below.
Returning to FIG. 2, the first high voltage circuit 20 includes the high voltage transistors NM0˜NM3. During an erase operation, gates of the high voltage transistors are coupled to 0V, which prevents the high bitline voltage from being applied to nodes SO0 and SO1 that are positioned in a low voltage field. However, undesirable leakage currents may still be generated in the layout structure with narrower bitline pitches that cause a high voltage to be forwarded into the low voltage field.
FIG. 3 is a diagram illustrating a layout pattern of the first high voltage circuit 20 of FIG. 2. Referring to FIG. 3, the first high voltage circuit 20 may be compartmented into a high voltage field and a low voltage field, in accordance with the dispositions of the high voltage transistors NM0˜NM3. During an erase operation, a voltage of 0V is applied to gates of the high voltage transistors NM0˜NM3. The portion of the bitlines BLe0, BLo0, BLe1, and BLo1 connected to the drains D0˜D3 of the transistors M0˜M3 belong to the high voltage field, while the portion of the bitlines connected to the nodes SO0 and SO1 belong to the low voltage field.
During an erase operation, the bitline BLe0 connected to a drain D0 of the high voltage transistor NM0 is operable in the low voltage field, while the bitline BLo0 connected to a drain D1 of the high voltage transistor NM1 is operable in the high voltage field. If a distance between a DC (Direct Contact) contact in the high voltage field and a bitline in the low voltage field is narrow, it may occur with an undesirable effect such as an oxide breakdown or a high voltage leakage between the high and low voltage fields when there have been misalignments or micro-bridges during a manufacturing process. The defective results arise from the fact that an electric field is enlarged in accordance with a narrower distance between the high and low voltage fields.
Further, while the node SO0 is being floated because the gate voltage of the high voltage transistor is 0V, a PMOS transistor PM0 of the page buffer 40 generates a leakage current without coupling by the high voltage because self-capacitance of the bitline is very larger than the coupling capacitance therebetween. Thus, the high voltage consumed by the leak current caused from a forward bias of a PN junction between the drain (P+) of the PMOS transistor and the bulk of N-well is discharged into the bulk region. This mechanism may cause undesirable reduction of the high voltage during an erase operation. Such a decrease of the high voltage applied to the bulk of the memory cells during an erase operation acts as a leading factor declining product yields and reliabilities.
In FIG. 2, the second high voltage circuit 30 includes the high voltage transistors NM4˜NM7. During an erase operation, 0V is applied to the gates of the high voltage transistors NM4˜NM7 in order to prevent the high bitline voltage from being forwarded into the low-voltage field. However, if the pitch (or distance) between the bitlines isolated from each other on the layout arrangement are narrow, undesirable leakage currents may occur resulting in a high voltage surge into the low-voltage field.
FIG. 4 is a diagram illustrating a layout pattern of the second high voltage circuit 30 of FIG. 2. Referring to FIG. 4, the high voltage circuit 30 is divided into a high voltage field and a low-voltage field. During an erase operation, 0V is applied to gates of the high voltage transistors. Here, the portion of the bitlines BLe0, BLo0, BLe1, and BLo1 connected between drains D4˜D7 of the transistors NM4˜NM7 and the memory cell array 10 are disposed in the high voltage field. The portion of the bitlines BLe0, BLo0, BLe1, and BLo1 connected between the virtual power node VIRPWR and the sources S4˜S7 of the transistors NM4˜NM7 are disposed in the low voltage field.
Because short distances exist between DC contacts of the high voltage field and bitlines of the low voltage field, an oxide breakdown or a high voltage discharge may occur between the high and low voltage fields during an erase operation if there are any misalignments or micro-bridges present from the manufacturing process. Such phenomena are induced by an electric field extending along the narrower spaces between the high and low voltage fields.
Furthermore, while the virtual power node VIRPWR is floated when the gate voltages of the high voltage transistors are at 0V, a high voltage may still be discharged through the PMOS transistor 51 without coupling thereto because the coupling capacitance is much larger than the self-capacitance of the bitline. In other words, the high voltage is discharged by way of a forward-biased PN junction between the N-well bulk and the P+ drain of the PMOS transistor 51 that is located in the bulk. This drop of high voltage during an erase operation is a significant factor contributing to the degradation in operational reliability of the flash memory device.
Embodiments of the invention address these and other disadvantages of the conventional art.